Integrated circuit arrangements with ever higher packing densities are being produced. The result of this is that interconnects in metallization levels are at an ever shorter distance from one another. This causes capacitances formed between the interconnects to rise, leading to long signal propagation times, a high power loss and undesired crosstalk, i.e. to interaction between signals applied to adjacent interconnects.
Silicon oxide, as a dielectric with a relative dielectric constant εr=3.9, is often used as insulation material between the interconnects.
What are known as low-k materials, i.e. materials with a low εr value, are used as material for intermetal dielectrics in order to reduce the relative dielectric constant εr, which leads to a drop in the level of the coupling capacitances between interconnects embedded in an insulation material.
It is also known from the prior art to produce cavities between interconnects within an interconnect level, in order to reduce the relative dielectric constant and therefore the coupling capacitance. The insulating dielectric, which determines the capacitance between the interconnects, in the region of cavities has a relative dielectric constant εr which is approximately equal to one. The interconnects themselves are surrounded by a layer of silicon oxide material or a low-k material in order to be decoupled from the surrounding area.
The high coupling capacitances C between adjacent interconnects, which become ever greater as circuits are increasingly miniaturized, together with the resistance R of an interconnect, lead to an RC switching delay for signals transported on the interconnects.
This RC switching delay can be reduced using airgaps as an alternative to low-k materials, since if airgaps are used between the interconnects, the effective dielectric constant εr as an insulating material between metallization tracks is considerably reduced. One possible implementation of airgaps is disclosed, for example, in Arnal, V et al., “Integration of a 3 Level Cu—SiO2 Airgap Interconnect for Sub 0.1 micron CMOS Technologies”, Proceedings IITC 2001.
Consequently, airgaps can be used to reduce the parasitic capacitance between metal tracks. However, a number of problems arise with the production of airgaps. Airgaps can be produced by means of anisotropic deposition of a dielectric on the metal tracks, with spaces in part remaining free of material between adjacent interconnects. However, this produces very long airgaps. Consequently, there is a risk of conflict with a metallization level above, for example when opening up the airgaps in a CMP (chemical mechanical polishing) process step, cf. Arnal, V et al. This risk is particularly high if the airgaps are not all of exactly the same width. This leads to considerable variation in the height of the airgaps.
According to the prior art, this problem can only be solved with considerable restrictions to the layout, namely by selecting all the distances between the metal tracks to be exactly equal. Alternatively, it is possible to introduce a process for forming airgaps with an additional lithography level, but this is expensive.
Furthermore, a region between adjacent interconnects with airgaps between them needs to be closed at the top, i.e. a sufficiently stable covering layer needs to be formed.
Arnal, V et al. describes a process in which electrically insulating material which has been introduced between electrically conductive interconnects is partially removed, in such a manner that airgaps are formed between the remainder of the electrically insulating material and the electrically conductive interconnects, the electrically conductive interconnects and the electrically conductive material being covered with a covering layer through which the evaporated electrically insulated material passes.
US 2002/0019125 A1 describes a process for copper metallization in which uncovered regions between the copper interconnects are then filled with an insulator layer, with an empty space in the insulator layer being formed in the filled regions between the copper interconnects.